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| IDT74SSTVF16857 14-BIT REGISTERED BUFFER WITH SSTL I/O COMMERCIAL TEMPERATURE RANGE 14-BIT REGISTERED BUFFER WITH SSTL I/O IDT74SSTVF16857 FEATURES: * * * * * * * * 2.3V to 2.7V Operation SSTL_2 Class I style data inputs/outputs Differential CLK input RESET control compatible with LVCMOS levels Flow-through architecture for optimum PCB design Drive up to equivalent of 14 SDRAM loads Latch-up performance exceeds 100mA ESD >2000V per MIL-STD-883, Method 3015; >200V using machine model (C = 200pF, R = 0) * Available in TSSOP package DESCRIPTION: The SSTVF16857 is a 14-bit registered buffer designed for 2.3V-2.7V VDD and supports low standby operation. All data inputs and outputs are SSTL_2 level compatible with JEDEC standard for SSTL_2. RESET is an LVCMOS input since it must operate predictably during the power-up phase. RESET, which can be operated independent of CLK and CLK, must be held in the low state during power-up in order to ensure predictable outputs (low state) before a stable clock has been applied. RESET, when in the low state, will disable all input receivers, reset all registers, and force all outputs to a low state, before a stable clock has been applied. With inputs held low and a stable clock applied, outputs will remain low during the Low-to-High transition of RESET. APPLICATIONS: * Along with CSPT857C, Zero Delay PLL Clock buffer, provides complete solution for DDR1 DIMMs FUNCTIONAL BLOCK DIAGRAM RESET 34 CLK CLK 38 39 VREF D1 35 48 1D C1 R 1 Q1 TO 13 OTHER CHANNELS COMMERCIAL TEMPERATURE RANGE 1 c 2003 Integrated Device Technology, Inc. The IDT logo is a registered trademark of Integrated Device Technology, Inc. JUNE 2003 DSC-6198/7 IDT74SSTVF16857 14-BIT REGISTERED BUFFER WITH SSTL I/O COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATION Q1 Q2 GND VDDQ Q3 Q4 Q5 GND VDDQ Q6 Q7 VDDQ GND Q8 Q9 VDDQ GND Q10 Q11 Q12 VDDQ GND Q13 Q14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 D1 D2 GND VDD D3 D4 D5 D6 D7 CLK CLK VDD GND ABSOLUTE MAXIMUM RATINGS (1) Symbol VDD or VDDQ VI (2) Description Supply Voltage Range Input Voltage Range Output Voltage Range Input Clamp Current, VI < 0 Output Clamp Current, VO < 0 or VO > VDDQ Continuous Output Current, VO = 0 to VDDQ Continuous Current through each VDD, VDDQ or GND Storage Temperature Range Max. -0.5 to 3.6 -0.5 to VDD +0.5 -0.5 to VDDQ +0.5 -50 50 50 100 -65 to +150 Unit V V V mA mA mA mA C VO(3) IIK IOK IO VDD TSTG VREF RESET D8 D9 D10 D11 D12 VDD GND D13 D14 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The input and output negative voltage ratings may be exceeded if the ratings of the I/P and O/P clamp current are observed. 3. The output current will flow if the following conditions are observed: a) Output in HIGH state b) VO = VDDQ FUNCTION TABLE (1) Input RESET H H H L CLK L or H X CLK L or H X D L H X X Q Outputs L H Qo(2) L TSSOP TOP VIEW NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = LOW to HIGH = HIGH to LOW 2. Qo = Output level before the indicated steady-state conditions were established. 2 IDT74SSTVF16857 14-BIT REGISTERED BUFFER WITH SSTL I/O COMMERCIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C, VDD = 2.5V 0.2V, VDDQ = 2.5V 0.2V Symbol VIK VOH VOL II IDD IDDD All Inputs Static Standby Static Operating Dynamic Operating (Clock Only) Dynamic Operating (Per Each Data Input) Data Inputs CI CLK and CLK RESET Parameter Control Inputs Test Conditions VDD = 2.3V, II = -18mA VDD = 2.3V to 2.7V, IOH = -100A VDD = 2.3V, IOH = -8mA VDD = 2.3V to 2.7V, IOL = 100A VDD = 2.3V, IOL = 8mA VDD = 2.7V, VI = VDD or GND IO = 0, VDD = 2.7V, RESET = GND IO = 0, VDD = 2.7V, RESET = VDD, VI = VIH (AC) or VIL (AC) IO = 0, VDD = 2.7V, RESET = VDD, VI = VIH (AC) or VIL (AC), CLK and CLK Switching 50% Duty Cycle. IO = 0, VDD = 2.7V, RESET = VDD, VI = VIH (AC) or VIL (AC), CLK and CLK Switching 50% Duty Cycle. One Data Input Switching at Half Clock Frequency, 50% Duty Cycle. VDD = 2.5V, VI = VREF 310mV VICR = 1.25V, VI (PP) = 360mV VI = VDD or GND 2.5 2.5 -- -- -- -- 3.5 3.5 -- pF -- -- -- Min. -- VDD - 0.2 1.95 -- -- -- -- -- -- Typ. -- -- -- -- -- -- -- 6 -- Max. -1.2 -- -- 0.2 0.35 5 0.01 -- -- A/Clock MHz A/Clock MHz/Data Input A mA V Unit V V OPERATING CHARACTERISTICS, TA = 25C (1) Symbol VDD VDDQ VREF VTT VI VIH VIL VIH VIL VIH VIL VICR VI (PP) IOH IOL TA Parameter Supply Voltage Output Supply Voltage Reference Voltage (VREF= VDDQ/2) Termination Voltage Input Voltage AC High-Level Input Voltage AC Low-Level Input Voltage DC High-Level Input Voltage DC Low-Level Input Voltage High-Level Input Voltage Low-Level Input Voltage Common-Mode Input Range Peak-to-Peak Input Voltage High-Level Output Current Low-Level Output Current Operating Free-Air Temperature Data Inputs Data Inputs Data Inputs Data Inputs RESET RESET CLK, CLK CLK, CLK Min. VDDQ 2.3 1.15 VREF- 40mV 0 VREF+ 310mV -- VREF+ 150mV -- 1.7 -- 0.97 360 -- -- 0 Typ.(1) -- 2.5 1.25 VREF -- -- -- -- -- -- -- -- -- -- -- -- Max. 2.7 2.7 1.35 VREF+ 40mV VDD -- VREF- 310mV -- VREF- 150mV -- 0.7 1.53 -- - 20 20 +70 C Unit V V V V V V V V V V V V mV mA NOTE: 1. The RESET input of the device must be held at VDD or GND to ensure proper device operation. 3 IDT74SSTVF16857 14-BIT REGISTERED BUFFER WITH SSTL I/O COMMERCIAL TEMPERATURE RANGE TIMING REQUIREMENTS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE VDD = 2.5V 0.2V Symbol CLOCK Parameter Clock Frequency Pulse Duration, CLK, CLK HIGH or LOW Differential Inputs Active Time Setup Time, Fast Slew Rate Hold Time, Fast Slew Rate (1) Min. -- 2.5 -- -- Data Before CLK, CLK Data Before CLK, CLK 0.75 0.9 0.75 0.9 Max. 200 -- 22 22 -- -- -- -- Unit MHz ns ns ns ns ns ns ns tw tACT tINACT tSU tN Differential Inputs Inactive Time(2) (3, 5) Setup Time, Slow Slew Rate(4, 5) (3,5) Hold Time, Slow Slew Rate(2,5) NOTES: 1. Data inputs must be low a minimum time of tACT max., after RESET is taken HIGH. 2. Data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT max., after RESET is taken LOW. 3. For data signal input slew rate is 1V/ns. 4. For data signal input slew rate is 0.5V/ns and <1V/ns. 5. CLK, CLK signal input slew rates are 1V/ns. SWITCHING CHARACTERISTICS OVER RECOMMENDED FREE-AIR OPERATING RANGE (UNLESS OTHERWISE NOTED) VDD = 2.5V 0.2V Symbol fMAX tPD tPHL Parameter CLK and CLK to Q RESET to Q Min 200 1.1 -- Max. -- 2.8 5 Unit MHz ns ns 4 IDT74SSTVF16857 14-BIT REGISTERED BUFFER WITH SSTL I/O COMMERCIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS (VDD = 2.5V 0.2V) VTT RL = 50 From Output Under Test Test Point CL = 30 pF (see note 1) Load Circuit LVCMOS RESET Input tINACT IDD (see note 2) VDD VDD/2 VDD/2 tACT 10% 90% 0V Timing Input tPLH Output VICR VICR tPHL VI(PP) VOH VTT VTT VOL Voltage and Current Waveforms Inputs Active and Inactive Times Voltage Waveforms - Propagation Delay Times LVCMOS RESET Input tW VIH Input VREF VREF Output VIL VIH VDD/2 VIL tPHL VOH VTT VOL Voltage Waveforms - Pulse Duration Voltage Waveforms - Propagation Delay Times Timing Input tSU Input VREF VICR VI(PP) tN VIH VREF VIL Voltage Waveforms - Setup and Hold Times NOTES: 1. CL includes probe and jig capacitance. 2. IDD tested with clock and data inputs held at VDD or GND, and IO = 0mA. 3. All input pulses are supplied by generators having the following characteristics: PRR 10MHz, ZO = 50, input slew rate = 1 V/ns 20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. VTT = VREF = VDDQ/2 6. VIH = VREF + 310mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input. 7. VIL = VREF - 310mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input. 8. tPLH and tPHL are the same as tPD. 5 IDT74SSTVF16857 14-BIT REGISTERED BUFFER WITH SSTL I/O COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XX SSTV XX Family Temp. Range XXXX XX Device Type Package PA PAG 857 Thin Shrink Small Outline Package TSSOP - Green 14-Bit Registered Buffer with SSTL I/O 16 74 Double-Density 0C to +70C CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com for Tech Support: logichelp@idt.com (408) 654-6459 6 |
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